{"id":1639,"date":"2013-07-25T18:26:16","date_gmt":"2013-07-25T18:26:16","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/?p=1639"},"modified":"2013-07-25T18:30:15","modified_gmt":"2013-07-25T18:30:15","slug":"towards-a-self-aligned-ingaas-trigate-mosfet","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/towards-a-self-aligned-ingaas-trigate-mosfet\/","title":{"rendered":"Towards a Self-aligned InGaAs Trigate MOSFET"},"content":{"rendered":"

Si-based CMOS technology is approaching the limits of its capabilities, and as a result there is extensive research into looking for novel methods to further scale logic circuitry. III-V semiconductors are considered leading candidates for future deeply-scaled integrated technology[1<\/a>]<\/sup>. The low-effective mass of various III-V materials such as InGaAs and InAs gives rise to extraordinarily high electron velocities, which promise transistors with high performance at low voltage.<\/p>\n

The fundamental requirement for future switches is simple: maximum ON current (ION<\/sub>) for a given OFF current (IOFF<\/sub>) operating at a small voltage on a sub-10-nm scale. Unfortunately, there is a tradeoff between ION<\/sub> and IOFF<\/sub> as the dimensions scale down. There are two approaches to address this problem. First, the material properties can be adjusted by means of strain management or alternative channel material; second, the dimensionality can be modified to obtain better electrostatic control and higher current density for a given footprint. III-V Trigate-FETs employ both approaches and are expected to show an unprecedented ION<\/sub>\/IOFF<\/sub> ratio at the 10-nm regime and under 0.5-V operation voltages.<\/p>\n

This project aims to demonstrate the first self-aligned sub-10-nm InGaAs Trigate transistor. There are many challenges to overcome before III-V Trigates can be accepted as a valid alternative. Understanding how to etch high aspect ratio fins, curing etching damage, reducing the sidewalls\u2019 interface state traps (Dit<\/sub>) and obtaining low access resistance are only few of the many difficulties that need to be faced. We are pursuing a device design and a process integration approach that will allow an aggressive scale-down of device dimensions. Figure 1 shows the fin- etch module test structure; we have fabricated InGaAs fins with sub-20-nm resolution using a novel RIE process.\u00a0 An aspect ratio as high as 10 and smooth sidewalls and surfaces have also been demonstrated (inset). Figure 2 shows the fin contacting scheme using Mo. To minimize the access resistance, the metal covers the source and drain top as well as the sidewalls.<\/p>\n

Successful demonstration of self-aligned III-V Trigate is an important milestone of CMOS technology, which will allow Moore\u2018s law to be extended, safely, into the sub-10-nm regime, and we are closer than ever to making it happen.<\/p>\n\n\t\t