{"id":1225,"date":"2013-07-25T18:24:46","date_gmt":"2013-07-25T18:24:46","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/?p=1225"},"modified":"2013-08-13T20:22:25","modified_gmt":"2013-08-13T20:22:25","slug":"statistical-modeling-with-the-virtual-source-mosfet-model","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/statistical-modeling-with-the-virtual-source-mosfet-model\/","title":{"rendered":"Statistical Modeling with the Virtual Source MOSFET Model"},"content":{"rendered":"

In this work, a statistical extension of the ultra-compact virtual source (VS) MOSFET model is developed here for the first time. The characterization uses a statistical extraction technique based on the backward propagation of variance (BPV) with variability parameters derived directly from the nominal VS model[1<\/a>]<\/sup>,[2<\/a>]<\/sup>. The resulting statistical VS model is extensively validated using Monte<\/p>\n

Carlo simulations and the statistical distributions of several figures of merit for logic, and memory cells are compared with those of a BSIM model from a 40-nm CMOS industrial design kit. The comparisons show almost identical distributions with distinct run time advantages for the statistical VS model. Additional simulations show that the statistical VS model accurately captures non-Gaussian features that are important for low-power designs.<\/p>\n

Figure 1 shows the key VS model parameters used for statistical modeling. The threshold voltage is modeled as \u00a0where \u00a0is the length-dependent DIBL coefficient. A special feature of the VS model is that is independent of the bias voltages. Previous work has shown that the relative change in virtual source velocity is related to the change in mobility.<\/p>\n

According to[1<\/a>]<\/sup>, also has a dependency on. Therefore variation on \u00a0also has an impact on. In the VS model, both effects are described using an approximation for the sensitivity of \u00a0with respect to \u00a0and. In the statistical extraction flow, variations \u00a0(i = 1, 2, \u2026, m) of electrical performance parameters (e.g., Idsat, Ioff , etc.) are measured under different geometry and bias conditions and the \u00a0are calculated from BPV according to the formula .<\/p>\n

To validate the accuracy of the VS statistical model as well as the statistical extraction method, we also implement it in Verilog-A. The resulting statistical VS model is validated using Monte Carlo simulations, and the statistical distributions of several figures of merits are compared with those of a BSIM model from a 40-nm CMOS industrial design kit. Figure 2 shows a fanout-of-3 static<\/p>\n

NAND2 gate operating under a \u00a0of 0.9V, 0.7V and 0.55V. Although all variation parameters in the VS model are assumed to be independent Gaussian variables, the non-Gaussian property of the delay distribution is correctly captured. The quantile-quantile plot for delay variation starts to deviate from a linear relationship when = 0.7V, and the non-linearity becomes pronounced at \u00a0= 0.55V.<\/p>\n\n\t\t