{"id":1178,"date":"2013-07-25T18:26:17","date_gmt":"2013-07-25T18:26:17","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/?p=1178"},"modified":"2013-07-25T18:26:17","modified_gmt":"2013-07-25T18:26:17","slug":"fabrication-technology-for-ingaasgaassb-vertical-tunnel-fets","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/fabrication-technology-for-ingaasgaassb-vertical-tunnel-fets\/","title":{"rendered":"Fabrication Technology for InGaAs\/GaAsSb Vertical Tunnel-FETs"},"content":{"rendered":"

With the continuing downscaling of the modern complementary metal\u2013oxide\u2013semiconductor<\/strong> (CMOS) technology, integrated circuit power consumption has become one of the most critical issues. This development is due to the limit of operation voltage scaling, which originates from the limit of 60mV\/dec sub-threshold swing in the conventional MOS devices[1<\/a>]<\/sup>. Various device structures have been proposed to achieve sub-threshold swing below 60mV\/dec using novel device physics, including impact ionization[2<\/a>]<\/sup>, interband tunneling[3<\/a>]<\/sup>, etc. In particular, tunnel-field-electron transistors (T-FETs) have attracted much attention due to their potential of achieving sharp subthreshold behavior, CMOS compatibility, and scalability[4<\/a>]<\/sup>. Vertical T-FETs with a heterojunction structure have been proposed to yield higher tunneling efficiency, and thus larger tunneling current[4<\/a>]<\/sup>, and are potential candidates for future-generation low-power technology. In this study, InGaAs\/GaAsSb heterojunction vertical T-FETs were designed and fabricated to investigate the impacts of different structural parameters.<\/p>\n

The cross-sectional view of the InGaAs\/GaAsSb vertical T-FET appears in Figure 1. The tunneling path from p+-GaAsSb to n-InGaAs is highlighted. To ensure complete gate control over the region where tunneling takes place, an air-bridge structure is implemented, eliminating potential leakage paths due to tunneling without gate-control. Figure 2 shows the proposed process flow. The molybdenum drain contact is deposited and patterned first, followed by mesa definition and etch. Then a HfO2<\/sub> gate dielectric and a tungsten gate are deposited after surface passivation. The air-bridge structure is formed by dry etching fins followed by a selective wet etch that undercuts the fin and suspends the air-bridges. Figure 2a shows an SEM micrograph of the air-bridge structure after lateral undercut etch. After the air-bridge formation, etching the n-InGaAs in the source region exposes the source. Then the Pd\/Au contact is deposited on the p+-GaAsSb layer. The inter-layer dielectric is then deposited, via holes are opened for contact, and finally, probe pads are formed. The impacts of different structural parameters on device performance are under study.<\/p>\n\n\t\t