{"id":1157,"date":"2013-07-10T16:03:49","date_gmt":"2013-07-10T16:03:49","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/?p=1157"},"modified":"2013-07-25T18:26:15","modified_gmt":"2013-07-25T18:26:15","slug":"a-ballistic-transport-model-for-iii-v-hemts-and-mosfets","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/a-ballistic-transport-model-for-iii-v-hemts-and-mosfets\/","title":{"rendered":"A Ballistic Transport Model for III-V HEMTs and MOSFETs"},"content":{"rendered":"

As silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down in size, fundamental physical limits threaten the continued improvement on their logic performance. With silicon approaching these limits, MOSFETs designed with III-V semiconductors have emerged as promising candidates to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs allow both faster and more power efficient performance[1<\/a>]<\/sup>. However, one of the key challenges, particularly as devices continue to shrink, is to understand the importance of non-idealities in field-effect transistor (FET) structures. High-electron-mobility transistors (HEMTs) are III-V quantum-well FETs that can be used to explore many issues of relevance to future III-V MOSFETs. HEMTs are worthwhile transistors in their own right, but they are also simpler than III-V MOSFETs and therefore allow a more thorough exploration into the basic transport physics of a quantum-well III-V device.<\/p>\n

HEMT experimental data show that electrons travel ballistically at gate lengths of 30-40 nm, suggesting that a ballistic transport model will become only more accurate as channel lengths are scaled down to 10 nm. We investigate to what extent this is true in III-V MOSFETs and also study the impact of short channel effects and other parasitics inherent in a III-V design.<\/p>\n

To accomplish these goals, we have developed a flexible transistor model in MATLAB based on a ballistic theory of transport. The model uses, at its core, a one-dimensional, self-consistent Poisson-Schr\u00f6dinger simulation of the heterostructure of the transistor. We then add extrinsic device parameters such as source and drain parasitic resistances (RS<\/sub> and RD<\/sub>), as well as appropriate values for the drain-induced barrier lowering (DIBL) and a distribution of interface trap states across the band gap at the semiconductor-oxide interface (Dit<\/sub>). We first used HEMTs to calibrate the model\u2019s validity with regards to the current-voltage characteristics. Due to the absence of a gate oxide, HEMTs do not suffer from interface states. We then turned to the physics of relevance to III-V MOSFETs, particularly the effects of Dit<\/sub> on the C-V and I-V characteristics. We can use our model to extract trap density as a function of energy in the bandgap of the barrier semiconductor. \u00a0Figure 1 shows the C-V curves for a simulated MOSFET structure first with no Dit<\/sub>, and then fitted to an experimental C-V curve using the Dit<\/sub> distribution shown in Figure 2. The MOSFET used for this comparison is an Al2<\/sub>O3<\/sub> buried-channel device fabricated by Lin et al. and described in[2<\/a>]<\/sup>. Ultimately, the ability to correctly model and predict device behavior will help identify the problems that need attention in the iterations of future device fabrication.<\/p>\n\n\t\t