{"id":5920,"date":"2012-07-18T22:26:46","date_gmt":"2012-07-18T22:26:46","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5920"},"modified":"2012-07-18T22:26:46","modified_gmt":"2012-07-18T22:26:46","slug":"designing-complex-digital-systems-with-nano-electro-mechanical-relays","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/designing-complex-digital-systems-with-nano-electro-mechanical-relays\/","title":{"rendered":"Designing Complex Digital Systems with Nano-electro-mechanical Relays"},"content":{"rendered":"

Silicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to sub-threshold leakage. Once this limit is reached, power constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternative device with steeper sub-threshold slope \u2013 i.e., lower VDD<\/sub>\/Ion<\/sub> for the same Ion<\/sub>\/Ioff<\/sub>. One promising class of such devices is electro-statically actuated nano-electro-mechanical (NEM) switches with nearly ideal Ion<\/sub>\/Ioff<\/sub> characteristics. Although mechanical movement makes NEM switches significantly slower than CMOS, they can be useful for a wide range of VLSI applications by reexamining traditional system- and circuit-level design techniques to take advantage of the electrical properties of the device. NEM relay circuits with pass-transistor logic design combine as many propagating electrical delays into as few mechanical delays as possible, parallelizing the tasks to do more operations in less time.<\/p>\n

Basic circuit design techniques and functionality of some main building blocks of VLSI systems, such as logic, memory, and clocking structures, have been successfully demonstrated in our previous works [1<\/a>] <\/sup> [2<\/a>] <\/sup> [3<\/a>] <\/sup>.<\/p>\n

Recently, complex arithmetic units such as relay-based multipliers have been developed (Figure 1b-c) [4<\/a>] <\/sup>. Simulation results of an optimized 16-bit relay multiplier built in a scaled relay process predicts ~10x improvement in energy-efficiency over optimized CMOS designs in the 10-100 MOPS performance range. The relative performance of the multiplier enhancements are in line with what was previously predicted by a NEM relay 32-bit adder [3<\/a>] <\/sup>, suggesting that complete VLSI systems (e.g., a microprocessor or an ASIC) would expect to see similar energy\/performance improvements from adopting NEM relay technology [3<\/a>] <\/sup> [4<\/a>] <\/sup>. The operation of the main building block of the MEM-relay based multiplier, the (7:3) compressor, is experimentally demonstrated. This circuit, consisting of 98 MEM-relays, is the largest MEM-relay based circuit successfully tested to date (Figure 2) [4<\/a>] <\/sup>.<\/p>\n\n\t\t