{"id":5915,"date":"2012-07-18T22:26:46","date_gmt":"2012-07-18T22:26:46","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5915"},"modified":"2012-08-06T16:01:28","modified_gmt":"2012-08-06T16:01:28","slug":"building-compressed-sensing-systems-sensors-and-analog-information-converters","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/building-compressed-sensing-systems-sensors-and-analog-information-converters\/","title":{"rendered":"Building Compressed Sensing Systems: Sensors and Analog Information Converters"},"content":{"rendered":"

Compressed sensing (CS) is a promising method for recovering sparse signals from fewer measurements than ordinarily used in Shannon\u2019s sampling theorem [1<\/a>] <\/sup> [2<\/a>] <\/sup>. One of the interesting applications of CS is in wireless sensors. Based on recent research, CS shows promise as a potential data compression scheme for wireless sensors. The other application of CS is in analog-to-information converters (AIC).\u00a0 For applications where signal frequencies are high, but information rates are low, AICs have been proposed as a potential solution to overcome the resolution and performance limitations of traditional, Nyquist-rate high-speed analog-to-digital converters (ADC), whose performance and resolution are often limited by circuit impairments such as sampling jitter and aperture [3<\/a>] <\/sup>.<\/p>\n

In this project, we have examined the energy-performance design space for CS in the context of both practical wireless sensor systems and AIC. We have shown that a CS-based sensor system can be an efficient and robust source encoding\/compression algorithm for wireless sensor applications where the signal of interest is sparse. As an ADC does, CS provides a flexible and general interface yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. CS can enable over 10X reduction in transmission energy when compared to raw quantized data. Furthermore, CS is robust to channel errors and amenable to error control schemes (e.g. CRC error detection) that enable 4X energy reduction and yet have simple hardware realizations [4<\/a>] <\/sup>. In the context of AIC, we have shown that the currently proposed AICs have no advantage over high-speed ADCs. Figure 1 shows an example of AIC architecture that facilitates slower ADCs (i.e. sub-Nyquist ADCs). However, the signal encoding, typically realized with a mixer-like circuit, still needs to occur at the Nyquist frequency of the input to avoid aliasing. The jitter and aperture in the mixer stage of AICs is found to similarly limit the resolution of AICs. Although the evaluation shows that this AIC architecture has limited resolution similar to high-speed ADCs, it has the potential to enable roughly a 2-10X reduction in power for applications where low amplifier gain\u00a0 is acceptable and the input signal is very sparse (see Figure 2) [5<\/a>] <\/sup>.<\/p>\n\n\t\t