{"id":5811,"date":"2012-07-18T22:27:17","date_gmt":"2012-07-18T22:27:17","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5811"},"modified":"2012-08-01T19:10:47","modified_gmt":"2012-08-01T19:10:47","slug":"technology-development-for-gan-and-si-integration","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/technology-development-for-gan-and-si-integration\/","title":{"rendered":"Technology Development for GaN and Si Integration"},"content":{"rendered":"

GaN is an excellent material to be used in high-power, high-frequency and high-temperature applications due to its wide band gap, high saturation velocity, etc. The monolithic integration of GaN power and\/or high frequency devices with Si CMOS digital ICs would enable a new level of circuit design flexibility [1<\/a>] <\/sup>. However, typically the GaN device fabrication uses different process technologies from the standard CMOS technologies in Si foundries, such as the Au-contained ohmic process. To realize the target of GaN and Si CMOS integration, Si-CMOS compatible process technologies need to be developed. For the first step, we endeavor to find an Au-free ohmic contact recipe with low contact resistance and smooth metal surface.<\/p>\n

The samples we used in this work have a 3-nm GaN cap, a 20-nm unintentionally doped AlGaN barrier layer, and a GaN buffer layer grown on a 6-inch Si wafer. Mesa isolation was realized using ICP systems with Cl2<\/sub>\/BCl3<\/sub> gases. For the ohmic contact, we tried different metal schemes including Ti\/Al, Ti\/Al\/Ti, Ti\/Al\/Pt, Ti\/Al\/Ni\/Pt, Ti\/Ge\/Ti\/Al\/Ni\/Pt, Si\/Ti\/Al\/Ti\/Ta, Mo\/Al\/Mo\/Ti, Ta\/Al\/Ta, Ta\/Al\/Ni\/Ta, etc, with different annealing temperatures varying from 500\u00b0C to 975\u00b0C using rapid thermal annealing (RTA) in N2<\/sub> ambience. We also tried to include a shallow recess using low etch-rate SiCl4<\/sub> plasma etch in an ICP system to improve the ohmic contact. Among these recipes, the metal scheme of Ti\/Al\/Ni\/Pt is found to give a relatively low contact resistance with very good metal surface. Lower ohmic contact resistance values together with a smooth metal surface can be obtained if a 20-30-nm recess is added.<\/p>\n

Figure 1 shows the optical pictures of the ohmic metal surface after RTA for 30 s for metal schemes of Ti\/Al\/Ni\/Au, Ti\/Al\/Ni\/Pt, and Ti\/Al\/Ni\/Pt with recess. The Au-contained recipe shows a very rough surface even it is annealed at a relatively low temperature of 800\u00b0C. The intermixing of Al and Au and the formation of viscous AlAu4<\/sub> phase are believed to result in the rough surface [2<\/a>] <\/sup>. Without Au, the metal surface of Ti\/Al\/Ni\/Pt is very smooth even it is annealed at a much high temperature up to 950\u00b0C. The recess of 20 nm (and 30 nm, not shown here) has no obvious effect on the metal surface after annealing. Figure 2 shows the typical contact resistance (R<\/em>C<\/sub>) values measured using the transition length method (TLM). A low R<\/em>C<\/sub> of around 0.45 \u03a9-mm can be obtained for the normal Ti\/Al\/Ni\/Au recipe. The R<\/em>C<\/sub> value of Ti\/Al\/Ni\/Pt metal is higher (~2.0 \u03a9-mm), and it can decrease to 1.6\u03a9-mm with the recess of 20 nm. In the future, more work needs to be carried out to further lower the R<\/em>C <\/sub>and optimize the Au-free ohmic contact recipes.<\/p>\n\n\t\t