{"id":5749,"date":"2012-07-18T22:27:43","date_gmt":"2012-07-18T22:27:43","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5749"},"modified":"2012-07-18T22:27:43","modified_gmt":"2012-07-18T22:27:43","slug":"a-two-step-pipelined-triple-slope-adc","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/a-two-step-pipelined-triple-slope-adc\/","title":{"rendered":"A Two-step Pipelined Triple-slope ADC"},"content":{"rendered":"
High resolution and high speed in data converters are difficult to achieve at low power consumption levels [1<\/a>] <\/sup>. \u00a0 This is due to the fundamental limit imposed by thermal noise in high-resolution converters, among other factors.\u00a0 In order to increase the resolution of a thermal noise limited data converter by one bit while maintaining the same sampling frequency, the power consumption must quadruple [2<\/a>] <\/sup>.\u00a0 Therefore, it is advantageous to exploit the benefits provided by multiple converter architectures in order to create the most energy-efficient design possible.<\/p>\n