{"id":5650,"date":"2012-07-18T22:28:04","date_gmt":"2012-07-18T22:28:04","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5650"},"modified":"2012-07-18T22:28:04","modified_gmt":"2012-07-18T22:28:04","slug":"asymmetrically-strained-sistrained-ge-trigate-p-mosfets","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/asymmetrically-strained-sistrained-ge-trigate-p-mosfets\/","title":{"rendered":"Asymmetrically Strained Si\/Strained Ge Trigate p-MOSFETs"},"content":{"rendered":"

Uniaxial strained Ge \u201cnanobars\u201d are of interest for future sub-10nm gate length p-MOSFETs because of the excellent electrostatic control afforded by the non-planar device geometry and the potential for high hole velocity in the uniaxial strained Ge.\u00a0 In this work, asymmetrically strained Si\/strained Ge trigate p-MOSFETs were fabricated from a strained germanium directly on insulator (SGDOI) substrate.\u00a0 The SGDOI substrate was fabricated using a bond and etchback technique that is depicted in Figure 1.\u00a0 An epitaxial wafer containing the desired final layers was bonded to a thermally oxidized Si handle wafer.\u00a0 The bonded wafer stack is then mechanically ground and chemically etched, leaving the desired final structure with the original grown-in strain intact.\u00a0 The wafer is processed to form p-MOSFETs using hybrid e-beam and photo-lithography to pattern nanobars and source\/drain pads, resulting in the final structure seen in the inset of Figure 2.\u00a0 The new free surfaces of the nanobars allow the originally biaxial strain to relax, causing asymmetric strain in the channel of the Ge trigate p-MOSFET.\u00a0 The gate oxide was formed by flowing ozone for passivation and depositing 40A HfO2<\/sub> and 200A WN as the gate electrode.\u00a0 The gate was used as a mask for ion implantation of boron, and standard CMOS processes was used for metallization. Figure 2 shows the transfer characteristics of a p-MOSFET with 18-nm-wide nanowires.<\/p>\n\n\t\t