{"id":5428,"date":"2012-07-18T22:28:42","date_gmt":"2012-07-18T22:28:42","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5428"},"modified":"2012-07-19T14:49:00","modified_gmt":"2012-07-19T14:49:00","slug":"a-quad-full-hd-high-efficiency-video-coding-decoder-chip","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/a-quad-full-hd-high-efficiency-video-coding-decoder-chip\/","title":{"rendered":"A Quad Full HD High Efficiency Video Coding Decoder Chip"},"content":{"rendered":"
The ever-increasing demand for richer internet video content and larger video resolution has motivated work on algorithms that achieve higher compression without sacrificing visual quality. High Efficiency Video Coding (HEVC) [1<\/a>] <\/sup> is being developed by the Joint Collaborative Team on Video Coding as a successor to the popular H.264\/MPEG-4 AVC standard. For the same quality, HEVC aims for a 50% bit-rate savings over AVC. This improvement comes at the cost of larger coding units, increased complexity through the addition of new coding tools, and increased computation in existing tools.<\/p>\n Key features of HEVC include hierarchical coding structures of sizes 64×64 down to 8×8 pixels, 36 intra-prediction modes, asymmetric motion partitions, large and non-square transforms, and multiple concatenated loop filters. This work aims at developing a new system architecture for the hierarchical coding structure along with novel designs for the coding tools themselves. A hybrid system pipeline structure is proposed to support all three largest coding units. The transform block uses SRAM-based 2-D transpose memory and leverages DCT matrix properties for extensive resource-sharing techniques for area reduction. External memory bandwidth and power are major concerns for high definition video decoding. These goals are addressed by a novel cache design with 2-D memory mapping and high throughput.<\/p>\n An HEVC video decoder chip capable of real time Quad Full HD (3840×2160) at 30 fps has been implemented. The decoder supports the HEVC Test Model HM-4.0 with low-complexity entropy coding and both low-delay and random-access encoding profiles.<\/p>\n