{"id":5184,"date":"2012-06-28T18:55:07","date_gmt":"2012-06-28T18:55:07","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/?p=5184"},"modified":"2012-07-18T22:29:32","modified_gmt":"2012-07-18T22:29:32","slug":"self-aligned-sub-100-nm-ingaas-mosfets-for-logic-applications","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2012\/self-aligned-sub-100-nm-ingaas-mosfets-for-logic-applications\/","title":{"rendered":"Self-aligned Sub-100-nm InGaAs MOSFETs for Logic Applications"},"content":{"rendered":"

InGaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown great potential for future high- performance and low-power logic applications [1<\/a>] <\/sup>.\u00a0 Superior electron transport properties [2<\/a>] <\/sup> and impressive device prototypes have been recently demonstrated [3<\/a>] <\/sup> [4<\/a>] <\/sup>. The parasitic resistance is an important problem to address, especially in deeply scaled devices. In addition, the gate-contact separation has to be kept to a minimum to achieve the device footprint goals. We address these requirements by introducing a novel transistor architecture with self-aligned contacts and a gate-last fabrication scheme.<\/p>\n

In this work, self-aligned InGaAs quantum-well MOSFETs in the sub-100-nm regime have been demonstrated. \u00a0A cross- sectional SEM image of a device with gate length of 90 nm is shown in Figure 1. As shown, the S\/D metal (Mo) and the n+<\/sup> cap are self-aligned to the gate. With an optimized recess etch process, the device has achieved a very tight S\/D-to-channel spacing (Lside<\/sub> < 20 nm). The channel consists of an InGaAs quantum well buried under a thin InP layer. A composite dielectric consisting of thin layers of Al2<\/sub>O3<\/sub> and HfO2<\/sub> is grown by atomic layer deposition (ALD).\u00a0 Well-behaved output characteristics are shown in Figure 2 for a 90-nm-gate length device. The total on-resistance of this device at Vgs<\/sub>-Vt<\/sub>= 0.7 V is 595 W.mm which is an excellent value. The subthreshold swing for a 60-nm-gate device at Vds<\/sub> = 0.5 V is 120 mV\/dec. The gate current is below 3×10-3<\/sup> A\/cm2<\/sup> at the maximum operating voltage (Vgs<\/sub>-Vt<\/sub> =0.7 V). The process yields devices with gate lengths down to 30 nm with acceptable parasitic resistance. This self-aligned architecture will enable us to explore the scaling behavior and electron transport characteristics of InGaAs QW-MOSFETs in a dimensional range of interest for future CMOS.<\/p>\n\n\t\t