{"id":3880,"date":"2011-07-13T17:47:09","date_gmt":"2011-07-13T17:47:09","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3880"},"modified":"2011-07-21T14:35:18","modified_gmt":"2011-07-21T14:35:18","slug":"vladimir-stojanovic","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/vladimir-stojanovic\/","title":{"rendered":"Vladimir Stojanovi\u0107"},"content":{"rendered":"<div class=\"pf-content\"><h3>Collaborators<\/h3>\n<ul>\n<li>E. Alon, UC Berkeley<\/li>\n<li>K. Asanovic, UC Berkeley<\/li>\n<li>T.-J. King Liu, UC Berkeley<\/li>\n<li>A. Kavcic, U. Hawaii at Manoa<\/li>\n<li>D. Markovic, UC Los Angeles<\/li>\n<li>C-K. K. Yang, UC Los Angeles<\/li>\n<\/ul>\n<h3>Graduate Students<\/h3>\n<ul>\n<li>W. An, EECS<\/li>\n<li>F. Chen, Res. Asst., EECS<\/li>\n<li>H. Fariborzi, Res. Asst., EECS<\/li>\n<li>M. Georgas, Res. Asst., EECS<\/li>\n<li>J. Leu, Res. Asst., EECS<\/li>\n<li>Y. Li, Res. Asst., EECS<\/li>\n<li>Z. Li, Res. Asst., EECS<\/li>\n<li>B. Moss, Res. Asst., EECS<\/li>\n<li>R. Sredojevi\u0107, Res. Asst., EECS<\/li>\n<li>C. Sun, Res. Asst., EECS<\/li>\n<li>O. Uyar, Res. Asst., EECS<\/li>\n<\/ul>\n<h3>Publications<\/h3>\n<p>R. Sredojevi\u0107 and V. Stojanovi\u0107, \u201cFully-Digital Transmit Equalizer<br \/>\nwith Dynamic Impedance Modulation\u201d, [Invited] <em> IEEE of Journal<\/em><br \/>\n<em> Solid-State Circuits,<\/em> 25 pp., August 2011.<\/p>\n<p>S. Song and V. Stojanovi\u0107, \u201cA 6.25 Gb\/s Voltage-time Conversion Based<br \/>\nFractionally Spaced Linear Equalization Receiver for High-speed<br \/>\nLinks,\u201d <em>IEEE Journal of Solid-State Circuits<\/em>, vol. 46, no. 5, 15<br \/>\npages, May 2011.<\/p>\n<p>J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanovi\u0107, and R. J.<br \/>\nRam, \u201cLow-Loss Polysilicon Waveguides Suitable for Integration within<br \/>\na High-Volume Electronics Process,\u201d  in <em>Proceedings of Optical Society<br \/>\nof America \u2013 CLEO\/QELS Conference,<\/em> Baltimore, MD, 2 pp., May 2011.<\/p>\n<p>S.D. Vamvakos, V. Stojanovi\u0107, and B. Nikoli\u0107, \u201cDiscrete-Time, Linear<br \/>\nPeriodically Time-Variant Phase-Locked Loop Model for Jitter<br \/>\nAnalysis,\u201d I<em>EEE Transactions on Circuits and Systems-I,<\/em> 16 pp.,<br \/>\n2011.<\/p>\n<p>H. Kam, T.-J. K. Liu, V. Stojanovi\u0107, D. Markovi\u0107, and E. Alon, \u201cDesign, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic,\u201d <em>IEEE Transactions on Electron Devices<\/em>, vol. 58, no. 1, pp. 236-250, January 2011.<\/p>\n<p>J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovi\u0107, H. Li<sup>,<\/sup> J. Sun, T. Bonifield, R. Hollingsworth, F. X. K\u00e4rtner, H. I. Smith, V. Stojanovi\u0107, and R. J. Ram, \u201cNanophotonic integration in state-of-the-art CMOS foundries,\u201d <em>Optics Express<\/em>, vol. 19, no. 3, pp. 2335-2346, January 2011.<\/p>\n<p>M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T-J. K. Liu, D. Markovi\u0107, E. Alon, and V. Stojanovi\u0107, \u201cDemonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications,\u201c <em>IEEE Journal of Solid-State Circuits <\/em>[Invited], vol. 46, no. 1, pp. 308-320, January 2011.<\/p>\n<p>R. Sredojevi\u0107, and V. Stojanovi\u0107, \u201cDigital Link Pre-emphasis with Dynamic Driver Impedance Modulation\u201d, <em>IEEE Custom Integrated Circuits Conference<\/em>, San Jose, CA, pp. 1-4, September 2010.<\/p>\n<p>F. Chen, A. P. Chandrakasan, and V. Stojanovi\u0107, \u201cA Low-power Area-efficient Switching Scheme for Charge-sharing DACs in SAR ADCs\u201d, <em>IEEE Custom Integrated Circuits Conference<\/em>, San Jose, CA, pp. 1-4, September 2010.<\/p>\n<p>F. Chen, A. P. Chandrakasan, and V. Stojanovi\u0107, \u201cA Signal-agnostic Compressed Sensing Acquisition System for Wireless and Implantable Sensors\u201d, <em>IEEE Custom Integrated Circuits Conference<\/em>, San Jose, CA, pp. 1-4, September 2010.<\/p>\n<p>H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam. V. Pott, T-J. K. Liu, E. Alon, V. Stojanovi\u0107, and D. Markovi\u0107, \u201cAnalysis and Demonstration of MEM-Relay Power Gating\u201d, <em>IEEE Custom Integrated Circuits Conference<\/em>, San Jose, CA, pp. 1-4, September 2010.<\/p>\n<p>S. Beamer, C. Sun, Y-J. Kwon, A. Joshi, C. Batten, V. Stojanovi\u0107, and K. Asanovi\u0107, \u201dRe-architecting DRAM with Monolithically Integrated Silicon Photonics,\u201d <em>37th International Symposium on Computer Architecture<\/em> (ISCA-37), Saint-Malo, France, pp. 129-140, June 2010.<\/p>\n<p>B. Bond, B., Z. Mahmood, R. Sredojevi\u0107, Y. Li, A. Megretski, V. Stojanovi\u0107, Y. Avniel, and L. Daniel, \u201cCompact Modeling of Nonlinear Analog Circuits using System Identification via Semi-Definite Programming and Robustness Certification,\u201d <em>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, <\/em>vol. 29, no. 8, pp. 1149-1162, August 2010.<\/p>\n<p>B. Kim and V. Stojanovi\u0107, \u201cAn Energy-Efficient Equalized Transceiver for RC-Dominant Channels,\u201d <em>IEEE Journal of Solid-State Circuits<\/em>, vol.45, no.6, pp.1186-1197, June 2010.<\/p>\n<p>F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J.\u00a0Jeon, T-J. K. Liu, D. Markovi\u0107, V. Stojanovi\u0107, and E. Alon, \u201cDemonstration of Integrated Micro-Electro-Mechanical (MEM) Switch Circuits for VLSI Applications,\u201d <em>IEEE International Solid-State Circuits Conference<\/em>, San Francisco, CA, pp. 150-151, February 2010.** (<em>Winner of the 2010 ISSCC Jack\u00a0Raper\u00a0Award for Outstanding Technology-Directions Paper<\/em>).<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Circuit, interconnect, and system design with novel devices (CNTs, NEM relays, Si-photonics). Integration of novel devices into CMOS design flows and foundries. On-chip interconnects and high-speed off-chip interfaces (electrical, photonic). Modeling and analysis of noise and dynamics in circuits and systems. Application of optimization techniques to digital communications, analog and digital circuits. Digital communications and signal-processing architectures, clock generation and distribution, high-speed digital circuit design, VLSI and mixed-signal IC design.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[80],"tags":[68],"_links":{"self":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3880"}],"collection":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/comments?post=3880"}],"version-history":[{"count":4,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3880\/revisions"}],"predecessor-version":[{"id":4242,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3880\/revisions\/4242"}],"wp:attachment":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/media?parent=3880"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/categories?post=3880"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/tags?post=3880"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}