{"id":3565,"date":"2011-07-08T15:13:05","date_gmt":"2011-07-08T15:13:05","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3565"},"modified":"2011-07-19T20:44:01","modified_gmt":"2011-07-19T20:44:01","slug":"design-and-demonstration-of-integrated-micro-electro-mechanical-mem-relay-power-gating","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/design-and-demonstration-of-integrated-micro-electro-mechanical-mem-relay-power-gating\/","title":{"rendered":"Design and Demonstration of Integrated Micro-electro-mechanical (MEM) Relay Power Gating"},"content":{"rendered":"

Power gating has become ubiquitous in ICs to reduce the power consumed by inactive CMOS logic circuits. However, the finite Ion<\/sub>\/Ioff<\/sub> ratio of MOSFET power gates limits their ability to reduce off-state leakage. In contrast, as described in [1<\/a>] <\/sup> [2<\/a>] <\/sup>, micro-electro-mechanical- (MEMS-) based power gates that mechanically make or break electrical contact can completely eliminate off-state leakage (Figure 1). The leakage benefits of MEMS-based power gates may be outweighed by increased switching energy and voltage droop due to relatively large device dimensions and\/or operating voltages and on-state resistance. A simple analysis is presented to predict the conditions under which electrostatically-actuated MEM relays can achieve energy savings over MOSFETs for power gates [3<\/a>] <\/sup>. This analysis shows that even in their current state of technology \u00a0(~100-\u03bcm device pitch), MEM relays can provide energy-reduction benefits over MOSFET power gates for off-periods > 500 \u03bcs. With relays scaled to current mass-produced MEMS device dimensions (~ 20 \u03bcm), the minimum off-period for energy-reduction benefit reduces to 10 \u00b5s.<\/p>\n

Relay reliability is improved by the use of hard metals, which results in relatively high contact resistance. For a given relay size, this resistance limits the current density that an array of relay power gates can deliver while maintaining the optimal voltage drop. Current relays can deliver up to ~1 mA\/mm2<\/sup> current density. However, power gates built from moderately scaled relays would support > 10-100 mA\/mm2<\/sup> and would still fit into the same area as the CMOS chip they are driving. The relays could therefore be post-fabricated on top of the chip or integrated into the backend metallization layers with no penalty in the overall die area.<\/p>\n

To experimentally demonstrate the feasibility of power-gating with current relay technology, we applied MEM relay power gating to a 90-nm CMOS chip operating at VDD = 0.6-1 V (Ion = 10-25 \u00b5A). Figure 2 illustrates the waveforms of the MEM relay power-gating this chip with MEM gate voltages VG<\/sub> swinging between 5 and 7 V, with the inset indicating the chip\u2019s correct I\/O activity during Ton<\/sub>.<\/p>\n\n\t\t