{"id":3524,"date":"2011-07-07T20:46:54","date_gmt":"2011-07-07T20:46:54","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3524"},"modified":"2011-07-28T15:19:51","modified_gmt":"2011-07-28T15:19:51","slug":"a-low-power-32-channel-digitally-programmable-neural-recording-system-2","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/a-low-power-32-channel-digitally-programmable-neural-recording-system-2\/","title":{"rendered":"A Low-power 32-channel Digitally-programmable Neural Recording System"},"content":{"rendered":"<div class=\"pf-content\"><p>We have designed an ultra-low-power 32-channel neural recording system in a 0.18-\u00b5m CMOS technology. The system consists of eight neural recording modules; each module contains four neural amplifiers, an analog multiplexer, an A\/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier&#8217;s input-referred noise to suit the background noise at the recording site. The amplifier&#8217;s input-referred noise can be adjusted from 11.2 \u00b5V<sub>rms<\/sub> (total power of 5.4 \u00b5W) down to 5.4 \u00b5V<sub>rms<\/sub> (total power of 20 \u00b5W) in the spike recording setting. The ADC in each recording module digitizes the signal from each amplifier at 8-bit precision with a sampling rate of 31.25 kS\/s per channel and an average power consumption of 483 nW per channel. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ\/State, making it one of the most energy-efficient designs for neural recording applications. The presented system was successfully tested in an <em>in-vivo<\/em> wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 \u00b5W. The neural amplifier and the ADC occupy the areas of 0.03 mm<sup>2<\/sup> and 0.02 mm<sup>2<\/sup>, respectively, making our design simultaneously area-efficient and power-efficient.<\/p>\n\n\t\t<style type=\"text\/css\">\n\t\t\t#gallery-1 {\n\t\t\t\tmargin: auto;\n\t\t\t}\n\t\t\t#gallery-1 .gallery-item {\n\t\t\t\tfloat: left;\n\t\t\t\tmargin-top: 10px;\n\t\t\t\ttext-align: center;\n\t\t\t\twidth: 50%;\n\t\t\t}\n\t\t\t#gallery-1 img {\n\t\t\t\tborder: 2px solid #cfcfcf;\n\t\t\t}\n\t\t\t#gallery-1 .gallery-caption {\n\t\t\t\tmargin-left: 0;\n\t\t\t}\n\t\t\t\/* see gallery_shortcode() in wp-includes\/media.php *\/\n\t\t<\/style>\n\t\t<div id='gallery-1' class='gallery galleryid-3524 gallery-columns-2 gallery-size-thumbnail'><dl class='gallery-item'>\n\t\t\t<dt class='gallery-icon landscape'>\n\t\t\t\t<a href='https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-content\/blogs.dir\/10\/files\/2011\/07\/Fig1.jpg' rel=\"lightbox[3524]\"><img width=\"130\" height=\"130\" src=\"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-content\/blogs.dir\/10\/files\/2011\/07\/Fig1-150x150.jpg\" class=\"attachment-thumbnail size-thumbnail\" alt=\"Figure 1\" loading=\"lazy\" aria-describedby=\"gallery-1-3525\" \/><\/a>\n\t\t\t<\/dt>\n\t\t\t\t<dd class='wp-caption-text gallery-caption' id='gallery-1-3525'>\n\t\t\t\tFigure 1: System architecture of the 32-channel neural recording IC.\n\t\t\t\t<\/dd><\/dl><dl class='gallery-item'>\n\t\t\t<dt class='gallery-icon landscape'>\n\t\t\t\t<a href='https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-content\/blogs.dir\/10\/files\/2011\/07\/Fig2.jpg' rel=\"lightbox[3524]\"><img width=\"130\" height=\"130\" src=\"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-content\/blogs.dir\/10\/files\/2011\/07\/Fig2-150x150.jpg\" class=\"attachment-thumbnail size-thumbnail\" alt=\"Figure 2\" loading=\"lazy\" aria-describedby=\"gallery-1-3526\" \/><\/a>\n\t\t\t<\/dt>\n\t\t\t\t<dd class='wp-caption-text gallery-caption' id='gallery-1-3526'>\n\t\t\t\tFigure 2: Superimposed digitized neural waveforms from one of the recording channels.\n\t\t\t\t<\/dd><\/dl><br style=\"clear: both\" \/>\n\t\t<\/div>\n\n<ol class=\"footnotes\">\n<li>W. Wattanapanitch and R. Sarpeshkar, \u201cA low-power 32-channel digitally-programmable neural recording system,\u201d\u00a0 <em>IEEE Transaction on Biomedical Circuits and Systems<\/em>, 2011, accepted for publication.<\/li>\n<\/ol>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>We have designed an ultra-low-power 32-channel neural recording system in a 0.18-\u00b5m CMOS technology. The system consists of eight neural&#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[26,5530],"tags":[65],"_links":{"self":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3524"}],"collection":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/comments?post=3524"}],"version-history":[{"count":10,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3524\/revisions"}],"predecessor-version":[{"id":4276,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3524\/revisions\/4276"}],"wp:attachment":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/media?parent=3524"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/categories?post=3524"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/tags?post=3524"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}