{"id":3382,"date":"2011-07-05T21:08:12","date_gmt":"2011-07-05T21:08:12","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3382"},"modified":"2011-07-19T20:29:37","modified_gmt":"2011-07-19T20:29:37","slug":"on-chip-dynamic-programming-networks-design-in-tsv-based-3d-stacking-technology-2","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/on-chip-dynamic-programming-networks-design-in-tsv-based-3d-stacking-technology-2\/","title":{"rendered":"On-chip Dynamic Programming Networks Design in TSV-Based 3D Stacking Technology"},"content":{"rendered":"

Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided an implementation platform for powerful multicore, multiprocessor, and network-on-chip (NoC) systems. As the communication complexity grows significantly with the number of computational, control, and memory units, design considerations and the provision for efficient interconnection in large-scale system will be critical. We have developed an on-chip distributed dynamic-programming (DP) network [1<\/a>] <\/sup> of transitivity computation on a 3D grid stack. Such type of network can be reconfigured for shortest path computation for finding optimal interconnected paths [1<\/a>] <\/sup> [2<\/a>] <\/sup> and with a range of applications including dynamic routing [3<\/a>] <\/sup>, deadlock detection [4<\/a>] <\/sup> and fault-tolerance [4<\/a>] <\/sup>. This abstract presents the design of a dynamic programming network, implemented in a fully stacked 3-layer 3D through silicon via (TSV<\/em>) 150-nm CMOS technology. This DP-network contains a 4\u00d74\u00d73 three-dimensional network. Three silicon layers contain a compact network of interconnected computational units. The vertical inter-unit communication is achieved by means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. The prototype circuit measures 2 mm\u00d72 mm. Test results demonstrated the effectiveness of such a DP-network for deadlock detection, and the computational delay is less than 10 ns for detecting deadlock from a large-scale network. This work provides promising results for future networks-on-chip applications using 3D embedded DP-network.<\/p>\n<\/div>

  1. T. Mak, K. P. Lam, H. S. Ng, G. Rachmuth, and C.-S. Poon, “A CMOS current-mode dynamic programming circuit,” IEEE Transactions on Circuits and Systems I-Regular Papers, <\/em>vol. 57, pp. 3112-3123, 2010. [↩<\/a>] [↩<\/a>]<\/li>
  2. K.-P. Lam, T. Mak, and C.-S. Poon, “Simulation of large-scale dynamic programming networks on 3D implementation platform,” presented at the Proc. of TENCON, Fukuoka, Japan, 2010. [↩<\/a>]<\/li>
  3. T. Mak, K.-P. Lam, P. Cheung, and W. Luk, “Adaptive routing in network-on-chips using a dynamic programming network,” IEEE Trans. Industrial Electronics,<\/em> accepted for publication. [↩<\/a>]<\/li>
  4. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, and M. Palesi, “Run-time deadlock detection in networks-on-chip using coupled transitive closure networks,” presented at DATE<\/em> – Design<\/em>, Automation<\/em> and<\/em> Test<\/em> in<\/em> Europe<\/em>, Grenoble, France, 2011. [↩<\/a>] [↩<\/a>]<\/li><\/ol>","protected":false},"excerpt":{"rendered":"

    Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided an implementation platform for powerful multicore, multiprocessor, and network-on-chip (NoC)…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[26,28,5530],"tags":[6242],"_links":{"self":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3382"}],"collection":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/comments?post=3382"}],"version-history":[{"count":3,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3382\/revisions"}],"predecessor-version":[{"id":4135,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3382\/revisions\/4135"}],"wp:attachment":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/media?parent=3382"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/categories?post=3382"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/tags?post=3382"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}