{"id":3199,"date":"2011-06-28T19:26:06","date_gmt":"2011-06-28T19:26:06","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3199"},"modified":"2011-07-19T20:17:50","modified_gmt":"2011-07-19T20:17:50","slug":"valence-band-offset-extraction-between-strained-si-and-strained-ge-layers","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/valence-band-offset-extraction-between-strained-si-and-strained-ge-layers\/","title":{"rendered":"Valence Band Offset Extraction Between Strained-Si and Strained-Ge Layers"},"content":{"rendered":"

The type-II band alignment between strained-silicon (s-Si) and strained-germanium (s-Ge) has been proposed for use in tunneling transistors due to the small effective band gap between the s-Si conduction band and s-Ge valence band [1<\/a>] <\/sup>. The small effective band gap may substantially increase tunneling current compared to a Ge homostructure while maintaining low off-state leakage. However, the valence band alignment between thin layers of s-Si and s-Ge on a relaxed SiGe substrate has not been experimentally extracted.<\/p>\n

The experimental device structure consists of an Al2<\/sub>O3<\/sub> high-\u03ba dielectric (~6 nm) on a Si capping layer (~ 6 nm) on s-Ge (~ 6 nm) grown pseudomorphically on a relaxed SiGe buffer (~1 \u00b5m) with 40% Ge concentration. The wafers were processed into MOS-capacitors and measured using low-frequency and quasistatic C-V techniques. The valence band offset can be extracted by fitting the simulation data to experimental C-V measurements [2<\/a>] <\/sup>. In Figure 1, the width of region II is dependent on the valence band offset and effective band gap between the s-Si and s-Ge layers.<\/p>\n

Figure 2 shows the band structure and hole density as a function of position for the fabricated structure. At 0 V gate voltage, most holes near the surface of the capacitor are contained in the s-Ge quantum well. Since the s-Ge quantum well is displaced from the Al2<\/sub>O3<\/sub> surface by the s-Si layer, the effective thickness is larger and thus the measured capacitance is lower than the oxide capacitance. As a more negative bias is applied to the gate, holes begin to accumulate at the s-Si\/Al2<\/sub>O3<\/sub> surface so that the total capacitance increases and approaches the oxide capacitance. The extracted valence band offset between the s-Si and s-Ge layers was 740\u00b130 meV, which also suggests a small effective band gap.<\/p>\n\n\t\t