{"id":3108,"date":"2011-06-28T15:29:37","date_gmt":"2011-06-28T15:29:37","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3108"},"modified":"2011-07-19T20:12:32","modified_gmt":"2011-07-19T20:12:32","slug":"platform-for-monolithic-integration-of-iii-v-devices-with-si-cmos","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/platform-for-monolithic-integration-of-iii-v-devices-with-si-cmos\/","title":{"rendered":"Platform for Monolithic Integration of III-V Devices with Si CMOS"},"content":{"rendered":"
\"Figure<\/a>

Figure 1: Cross-sectional TEM image of the SOLES structure.<\/p><\/div>\n

Monolithic integration of III-V devices with Si CMOS technology allows us to combine the unique capabilities of III-V devices with the economies of scale and established infrastructure of Si CMOS to create advanced circuits with new functionalities.\u00a0 We have developed the silicon-on-lattice-engineered-silicon (SOLES) substrate platform in order at accomplish this goal [1<\/a>] <\/sup> [2<\/a>] <\/sup> [3<\/a>] <\/sup> [4<\/a>] <\/sup>.\u00a0 The SOLES structure is a silicon substrate with an embedded III-V template.\u00a0 One version of it is illustrated in Figure 1.\u00a0 First, Si CMOS devices are fabricated on the top silicon-on-insulator layer due to their high thermal budget requirements.\u00a0 Once the Si devices are in place, the III-V template can be accessed by etching windows in the top Si and oxide.\u00a0 III-V device structures can then be grown from the III-V template to be coplanar with the CMOS devices.\u00a0 If these III-V devices are encapsulated with Si, CMOS silicide contacts can be made to both the Si and III-V in parallel.<\/p>\n

InP metamorphic heterojunction bipolar transistors (mHBTs) and Si CMOS devices have been successfully integrated on SOLES wafers, although with traditional III-V and CMOS contact technology [5<\/a>] <\/sup>.\u00a0 We are now working to establish a CMOS metallization scheme for III-V devices based on silicide technology.\u00a0 We are also developing improved versions of the SOLES structure, with direct incorporation of high quality III-V template layers.<\/p>\n<\/div>

  1. C. L. Dohrman, K. Chilukuri, D. M. Isaacson, M. L. Lee, and E. A. Fitzgerald, \u201cFabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices,\u201d Materials Science and Engineering B: Solid-State Materials for Advanced Technology<\/em>, vol. 135, no. 3, pp. 235-237, Dec. 2006. [↩<\/a>]<\/li>
  2. F. Letertre, \u201cFormation of III-V semiconductor engineered substrates using Smart CutTM layer transfer technology,\u201d in Mater. Res. Soc. Symp. Proc.<\/em> 2008, vol. 1068, pp. 1068-C01-01. [↩<\/a>]<\/li>
  3. K. Chilukuri, M. J. Mori, C. L. Dohrman, and E. A. Fitzgerald, \u201cMonolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES),\u201d Semiconductor Science and Technology<\/em>, vol. 22, pp. 29-34, 2007. [↩<\/a>]<\/li>
  4. N. Yang, M. T. Bulsara, E. A. Fitzgerald, W. K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wu, M. Urteaga, W. Ha, J. Bergman, B. Brar, C. Drazek, N. Daval, L. Benaissa, E. Augendree W. E. Hoke, J. R. LaRoche, K. J. Herrick, and T. E. Kazior, \u201cThermal considerations for advanced SOI substrates designed for III-V\/Si heterointegration,\u201d in 2009 IEEE International SOI Conference<\/em>, pp. 121-122. [↩<\/a>]<\/li>
  5. W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W.\u00a0 Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, \u201cMonolithic integration of InP-based transistors on Si substrates using MBE,\u201d J. Crystal Growth<\/em>, vol. 311, no. 7, pp. 1979\u20131983, Mar. 2009. [↩<\/a>]<\/li><\/ol>","protected":false},"excerpt":{"rendered":"

    Monolithic integration of III-V devices with Si CMOS technology allows us to combine the unique capabilities of III-V devices with…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[5528],"tags":[19,6194],"_links":{"self":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3108"}],"collection":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/comments?post=3108"}],"version-history":[{"count":3,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3108\/revisions"}],"predecessor-version":[{"id":4085,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/posts\/3108\/revisions\/4085"}],"wp:attachment":[{"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/media?parent=3108"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/categories?post=3108"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/wp-json\/wp\/v2\/tags?post=3108"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}