{"id":3098,"date":"2011-06-28T14:52:03","date_gmt":"2011-06-28T14:52:03","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=3098"},"modified":"2011-07-19T20:11:57","modified_gmt":"2011-07-19T20:11:57","slug":"fabrication-of-gaas-on-insulator-via-low-temperature-wafer-bonding-and-sacrificial-etching-of-ge-by-xef2","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/fabrication-of-gaas-on-insulator-via-low-temperature-wafer-bonding-and-sacrificial-etching-of-ge-by-xef2\/","title":{"rendered":"Fabrication of GaAs-on-Insulator via Low-temperature Wafer Bonding and Sacrificial Etching of Ge by XeF2"},"content":{"rendered":"

Front-end integration of III-V compound semiconductor devices with Si metal-oxide-semiconductor (MOS) technology requires the development of commercially viable engineered substrates [1<\/a>] <\/sup> [2<\/a>] <\/sup>. The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding, and layer exfoliation. \u00a0We report on the development of GaAs-on-insulator (GaAsOI) structures without the use of SmartcutTM<\/sup> technology. GaAs\/Ge\/GaAs epitaxial stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding [3<\/a>] <\/sup>.\u00a0 A room-temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate were realized through room-temperature, gas-phase lateral etching of an embedded Ge sacrificial layer by xenon difluoride (XeF2<\/sub>). Figure 1 schematically shows our fabrication process. This GaAsOI fabrication process is shown to be successful on a small scale. Figure 2 shows a cross-sectional TEM image of the final GaAsOI\/Si structure fabricated with this process. Implementation of this process for fabricating large-area GaAsOI substrates is currently limited by the long diffusion distances required in a wafer-scale lateral etching process.\u00a0 We established a model that identifies the rate-limiting processes and potential approaches that lift these constraints and enable this method to be used for fabrication of large-diameter GaAsOI substrates.<\/p>\n\n\t\t