{"id":2854,"date":"2011-06-23T19:28:09","date_gmt":"2011-06-23T19:28:09","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=2854"},"modified":"2011-07-19T15:31:58","modified_gmt":"2011-07-19T15:31:58","slug":"a-low-power-sar-adc-with-redundancy","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/a-low-power-sar-adc-with-redundancy\/","title":{"rendered":"A Low-power SAR ADC with Redundancy"},"content":{"rendered":"

Technology scaling has enabled low-power operations in digital integrated circuits.\u00a0 Therefore, the trend to move analog-to-digital operations upstream to allow more signal-processing to shift from the analog domain to the digital domain is inevitable. As most real world signals remain analog, the design of high-performance and low-power analog-digital converters (ADCs) plays a key role to the success of future integrated system design. In this research, we focus on designing (1) robust, (2) low-power, and (3) high-performance time-interleaved successive-approximation-registers (SAR) ADCs. The SAR architecture is adopted because of its good digital compatibility and high energy-efficiency while achieving high sampling rates.<\/p>\n

The robustness of SAR ADCs is achieved by analyzing the effectiveness of redundancy (digital error correction) [1<\/a>] <\/sup> [2<\/a>] <\/sup> in improving sampling rates and its immunity from incomplete bit settling errors. Analysis shows that the redundancy algorithm does not help improve sampling rate in all SAR ADC designs; instead, the maximum sampling rate depends on the settling time constant (\u03c4) and the relative magnitude of the ADC delay components [3<\/a>] <\/sup>. As shown in Figure 1, in order to benefit from the redundancy algorithm, \u03c4 has to be more than 50 ps.<\/p>\n

The low-power operation is achieved by combining the merged capacitor switching algorithm [4<\/a>] <\/sup> and split capacitive array [5<\/a>] <\/sup>. The merged capacitor switching algorithm suffers from its sensitivity to the parasitic capacitance on the outputs of the capacitive DAC. The split capacitive array suffers from a 4x loss in signal power to keep voltage below the supply rail on the sub-DAC and the mismatch problem between the fractional bridge capacitor to other capacitors in the DAC. Our design researches and resolves both issues. Our design also incorporated asynchronous on-chip pulse generator to avoid synchronous high power clock distribution circuit on-chip. The overall SAR ADCs architecture is depicted in Figure 2.<\/p>\n\n\t\t