{"id":2704,"date":"2011-06-19T13:10:26","date_gmt":"2011-06-19T13:10:26","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=2704"},"modified":"2011-07-28T15:15:45","modified_gmt":"2011-07-28T15:15:45","slug":"energy-delay-trade-off-for-devices-with-asymmetric-n-type-and-p-type-current-drives-from-a-static-cmos-circuit-level-perspective","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/energy-delay-trade-off-for-devices-with-asymmetric-n-type-and-p-type-current-drives-from-a-static-cmos-circuit-level-perspective\/","title":{"rendered":"Energy-delay Trade-off for Devices with Asymmetric n-type and p-type Current Drives from a Static-CMOS Circuit-level Perspective"},"content":{"rendered":"

Historically, digital logic devices are benchmarked by the on-state current (Ion<\/sub><\/em>) at specified off-state current (Ioff<\/sub><\/em>) and supply voltage (Vdd<\/sub><\/em>) at each technology node.\u00a0 Emerging device technologies are often targeted to outperform Si MOSFETs at the same Ioff<\/sub> <\/em>and Vdd<\/sub><\/em>.\u00a0 Some emerging technologies, such as III-V transistors and Ge transistors, have great advantages in either n-type or p-type devices, instead of both types, at the device level in terms of Ion<\/sub><\/em>.\u00a0 However, recent work [1] shows that devices optimized based on the conventional device-level Ion<\/sub><\/em> methodology may not necessarily give the best performance at the circuit-level.\u00a0 In this work, we extend the methodology proposed in\u00a0 [1<\/a>] <\/sup> to study the technologies with asymmetric n-type and p-type driving capabilities from a circuit-level perspective.<\/p>\n

Circuit-level delay and energy are calculated following the strategies described in [1<\/a>] <\/sup>, assuming static CMOS logic gates.\u00a0 The smaller of the widths of nMOS (Wn<\/sub><\/em>) and pMOS (Wp<\/sub><\/em>) is fixed to be 1 mm. <\/em> Assuming the same pull-up and pull-down delay, the P\/N ratio (k=Wp<\/sub>\/Wn<\/sub><\/em>), is adjusted according to the on-current.\u00a0\u00a0 Figure 1(a) minimizes energy per switch at each delay point for selected P\/N ratio, with a pMOS and nMOS transporting 10x and 1x current of the 11-nm projection device in [1<\/a>] <\/sup> at the same bias.\u00a0\u00a0 The corresponding dynamic energy (Edyn<\/sub>\u00ad<\/em>) over total energy (Etot<\/sub><\/em>) is shown in Figure 1(b).\u00a0\u00a0 It is shown that the optimal sizing ratio is not necessarily 1\/10 as in following the conventional sizing scheme.\u00a0 In fact, the optimal k<\/em> is the smallest number that can maintain Edyn<\/sub><\/em> at around 80% of Etot<\/sub><\/em>.\u00a0 As Figure 2 shows, compared with the baseline technology with symmetric nMOS and pMOS, the technology that improves the transport capability of only one type of devices hardly benefits the circuit-level energy-delay trade-off.
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