{"id":2696,"date":"2011-06-19T13:05:27","date_gmt":"2011-06-19T13:05:27","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=2696"},"modified":"2012-07-03T18:29:46","modified_gmt":"2012-07-03T18:29:46","slug":"hole-mobility-in-strained-ge-p-mosfets-with-high-kmetal-gate-stack-2","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/hole-mobility-in-strained-ge-p-mosfets-with-high-kmetal-gate-stack-2\/","title":{"rendered":"Hole Mobility in Strained-Ge p-MOSFETs with High-k\/Metal Gate Stack"},"content":{"rendered":"

The need for high speed and density in modern integrated circuits requires new MOSFET channel materials, techniques for improved carrier transport, and continuous scaling of the device dimensions. Strained-Ge is implemented in this work as a material for enhanced hole transport.\u00a0 A high-k dielectric and metal gate stack is used for improved electrostatic control. At present, incorporating an epitaxial Si capping layer between the high-k dielectric and the Ge is the most promising approach for achieving a high quality Ge-dielectric interface, with 10x hole mobility enhancement relative to Si control devices reported for p-MOSFETs using this approach [1<\/a>] <\/sup>.\u00a0 However, the use of a Si-cap leads to increased Capacitance Equivalent Thickness (CET) of the structure, which degrades electrostatic control.\u00a0 In addition, a Si cap provides a parasitic path for hole transport, which can deteriorate the effective hole mobility of the device at high inversion charge densities. Therefore, a process to fabricate MOSFETs by depositing a high-k dielectric directly on strained-Ge substrate should be developed and is the aim of this research.<\/p>\n

Strained-Ge MOSFETs with and without a Si-cap were fabricated to quantitatively assess the hole mobility and its dependence on dielectric interface quality. The gate stack for all the devices was 6-nm Al2<\/sub>O3<\/sub>\/30 nm WN. \u00a0Figure 1 shows the I-V characteristics of a strained-Ge MOSFET without a Si cap with the device cross-section shown in the inset. A very respectable on-to-off ratio is demonstrated for this long-channel (20-\u00b5m) device.\u00a0 Figure 2 shows the hole mobility for the devices with and without a silicon cap, compared to the universal mobility and previous results reported by Weber et al [2<\/a>] <\/sup>. The samples without a silicon cap showed relatively high hysteresis (~150 mV) and lower hole mobility than the Si-capped devices. However, the mobility enhancement observed for the sample without the Si cap is larger than reported values for relaxed or strained Ge without a Si cap [3<\/a>] <\/sup> [4<\/a>] <\/sup>.\u00a0 This result is promising and illustrates the need for continued investigation of methods for improved passivation of the strained-Ge surface prior to direct high-k dielectric deposition.<\/p>\n\n\t\t