{"id":2678,"date":"2011-06-19T13:02:27","date_gmt":"2011-06-19T13:02:27","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/?p=2678"},"modified":"2012-07-03T18:12:10","modified_gmt":"2012-07-03T18:12:10","slug":"a-self-aligned-ingaas-quantum-well-field-effect-transistor-for-logic-applications","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2011\/a-self-aligned-ingaas-quantum-well-field-effect-transistor-for-logic-applications\/","title":{"rendered":"A Self-aligned InGaAs Quantum-well Field-effect Transistor for Logic Applications"},"content":{"rendered":"

InGaAs is a promising candidate for channel material for future high-performance CMOS logic applications because of its superior electron transport properties [1<\/a>] <\/sup>. InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) research has recently attracted great interest from the IC device community. \u00a0N-channel InGaAs-based High-electron-mobility transistors (HEMTs) fabricated previously at MIT have served as an excellent testbed with which to explore issues of importance in a future III-V CMOS technology. They demonstrated outstanding logic device characteristics due to the high injection velocity at low supply voltage and high electrostatic integrity afforded by the quantum-well channel [1<\/a>] <\/sup> [2<\/a>] <\/sup> [3<\/a>] <\/sup>. These advantages, if ported over to InGaAs MOSFETs, can eventually lead to integrated circuits exhibiting high speed with reduced power dissipation.<\/p>\n

There are many challenges in the development of a InGaAs QW-MOSFET technology for future CMOS applications. For example, low series resistance and a compact footprint are required. In this work we prototype a novel self-aligned InGaAs QW-MOSFET that can address these problems. The cross-sectional schematic of the QW-MOSFET is shown in Figure 1. This device uses a thin Al2<\/sub>O3<\/sub> gate dielectric. Molybdenum-based ohmic contacts are self-aligned to the gate. This self-alignment scheme reduces the spacing between the contacts and the gate and leads to a lower series resistance. A first working prototype QW-MOSFET with Lg<\/sub><\/em> =2 mm has been fabricated, and the output characteristics are shown in Figure 2. Process optimization, aimed at a further reduction in the source resistance, is being carried out. The scaling behavior and performance analysis with respect to silicon technology for this new device structure will be investigated.<\/p>\n\n\t\t