{"id":748,"date":"2010-06-25T12:40:46","date_gmt":"2010-06-25T16:40:46","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=748"},"modified":"2010-06-29T15:06:45","modified_gmt":"2010-06-29T19:06:45","slug":"a-6-25-gbs-adaptive-fractionally-spaced-receive-equalizer-with-voltage-time-conversion","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/a-6-25-gbs-adaptive-fractionally-spaced-receive-equalizer-with-voltage-time-conversion\/","title":{"rendered":"A 6.25-Gb\/s Adaptive Fractionally Spaced Receive Equalizer with Voltage-time Conversion"},"content":{"rendered":"

This work describes an architecture and circuit implementation of a fractionally spaced equalizer (FSE) receiver [1<\/a>]<\/sup>, built to unify equalization and phase synchronization in high-speed links, as shown in Figure 1. To achieve the desired linearity for adaptation with good energy efficiency, large input dynamic range, and high operation rate, the FSE is designed using a voltage-time conversion technique [2<\/a>]<\/sup>. The proposed auto-zero inverter-based threshold detectors are able to compensate for the detection threshold mismatch while converting voltage signals to timing signals, a trait missing in [1<\/a>]<\/sup>. A two-tap quad-rate FSE receiver with one-tap DFE is fabricated in 90-nm bulk CMOS technology, occupying a 0.03 mm2<\/sup> active area.\u00a0 With a 1.2-V supply, it achieves a 6.25-Gbps rate, 3.6-pJ\/bit efficiency and 5 effective bits of linearity.<\/p>\n

A modified sign-sign LMS adaptive algorithm is used to tune the FSE tap weights to mitigate the inter-symbol interference (ISI) for the arbitrary receiver phase. Based on data conditioning, it reduces the quantization noise and overcomes divergence issues of the traditional FSE sign-sign LMS algorithm.<\/p>\n