{"id":735,"date":"2010-06-28T10:31:40","date_gmt":"2010-06-28T14:31:40","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=735"},"modified":"2010-07-22T11:31:31","modified_gmt":"2010-07-22T15:31:31","slug":"ssta-design-methodology-for-low-voltage-operation","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/ssta-design-methodology-for-low-voltage-operation\/","title":{"rendered":"SSTA Design Methodology for Low Voltage Operation"},"content":{"rendered":"
\"Figure<\/a>

Figure 1: Joint PDF of stage delays in the TP has sharp maxima in the D-space. The point of maxima is called the operating point. Non-linear delay curve can be linearized about the operating point and the TP delay can be given as a linear combination of individual stage delays at the operating point<\/p><\/div>\n

Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations [1<\/a>]<\/sup>. With transistor geometries shrinking below 65nm, however, a new kind of statistical variation, known as Local or Intra-die variation [2<\/a>]<\/sup> has become important for logic.<\/p>\n

In order to predict the statistical impact of local variations on circuit performance, it necessary to develop the statistical models that accurately reflect local variations and to develop a computationally efficient algorithm for performing SSTA using these models. This work develops an SSTA design methodology for low voltage operation. The approach is called Non-Linear Operating Point Analysis for Local Variations (NLOPALV) [3<\/a>]<\/sup>. It addresses different aspects of timing analysis starting from standard cell library characterization to full-chip timing closure.<\/p>\n

\"Figure<\/a>

Figure 2: TP delay PDF is highly non-Gaussian at low-voltages with 3-sigma stochastic delay comparable to or more than the nominal delay. The zero-sigma delay is the nominal delay. TP delay PDF peaks at a point less than the nominal delay. Gaussian approximation gives highly optimistic estimate of the 3-sigma TP delay.<\/p><\/div>\n

The goal of timing path (TP) analysis is to determine f<\/em>-sigma stochastic delay. Computational efficiency of the NLOPALV approach comes from the concept of operating point, which allows us to determine the f<\/em>-sigma TP delay without computing the entire delay PDF.\u00a0 Once the operating point is determined, the f<\/em>-sigma TP delay can be computed as a linear sum of individual stage delays computed at the operating point (Figure 1). The NLOPALV approach is integrated with commercial CAD flow and validated on a digital signal processor implemented using commercial 28nm CMOS technology (Figure 2).<\/p>\n

Any practical IC has millions of timing paths. In order to complete the timing analysis in an acceptable run-time, it is essential to reduce the number of paths that need to be analyzed. An approach to reduce the number of critical paths in a design has been developed using the concepts of NLOPALV. This approach can eliminate more than 95% of the paths in a very short run-time. The detailed NLOPALV analysis is then performed on the remaining paths to achieve timing closure for the IC.<\/p>\n

\r\nReferences
  1. A. Agarwal, D. Blaauw and V. Zolotov, \u201cStatistical timing analysis for intra-die process variations with spatial correlations,\u201d Computer Aided Design 2003, ICCAD-2003, International Conference on<\/em>, pp. 900-907, 2003. [↩<\/a>]<\/li>
  2. S. Sundareswaran., J. A. Abraham, A. Ardelea, R. Panda, \u201cCharacterization of Standard Cells for Intra-Cell Mismatch Variations\u201d, Proceedings of the 9th international Symposium on Quality Electronic Design<\/em>. March 17 – 19, 2008. [↩<\/a>]<\/li>
  3. R. Rithe, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, \u201cNon-linear operating point statistical analysis for local variations in logic timing at low voltage,\u201d Proceedings of Design Automation and Test in Europe,<\/em> pp. 965-968, March 2010. [↩<\/a>]<\/li><\/ol><\/div>","protected":false},"excerpt":{"rendered":"

    Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations [1]….<\/p>\n<\/div>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[26],"tags":[17,4242],"_links":{"self":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/735"}],"collection":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/comments?post=735"}],"version-history":[{"count":5,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/735\/revisions"}],"predecessor-version":[{"id":739,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/735\/revisions\/739"}],"wp:attachment":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/media?parent=735"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/categories?post=735"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/tags?post=735"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}