{"id":724,"date":"2010-06-25T12:20:29","date_gmt":"2010-06-25T16:20:29","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=724"},"modified":"2010-06-25T15:57:39","modified_gmt":"2010-06-25T19:57:39","slug":"sram-voltage-scaling-in-advanced-cmos-for-low-power","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/sram-voltage-scaling-in-advanced-cmos-for-low-power\/","title":{"rendered":"SRAM Voltage-scaling in Advanced CMOS for Low Power"},"content":{"rendered":"

There is a need for large embedded memory that operates over a wide range of supply voltage compatible with the limits of static CMOS that also minimizes active and standby power. The technical challenge lies at the intersection of low-voltage operation and process variation. This work develops both statistical methods to efficiently design static random access memory (SRAM) and test chip prototypes.<\/p>\n

A simulation methodology incorporating new techniques, known as \u201cloop flattening\u201d and \u201cspherical sampling,\u201d demonstrates the capability to evaluate SRAM read-access yield with speedups of 650x more [1<\/a>]<\/sup>. It overcomes key challenges related to both the complex interconnections in the read path and conducting Importance Sampling simulation in a high-dimensionality parameter space (Figure 1).<\/p>\n

Additionally, an 8T SRAM fabricated in 45nm SOI CMOS exhibits voltage scalable operation from 1.2V down to 0.57V with access times from 400ps to 3.4ns [2<\/a>]<\/sup>. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier (ACSA) (Figure 2). An area-efficient data path is achieved with a regenerative global bitline scheme. Finally, a data-retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the content of the memory (Figure 3).<\/p>\n\n\t\t