{"id":680,"date":"2010-06-25T11:02:36","date_gmt":"2010-06-25T15:02:36","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=680"},"modified":"2010-06-28T16:12:15","modified_gmt":"2010-06-28T20:12:15","slug":"integrated-graphene-interconnects-with-cmos","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/integrated-graphene-interconnects-with-cmos\/","title":{"rendered":"Integrated Graphene Interconnects with CMOS"},"content":{"rendered":"
As process technology scales, the importance of material and architectural innovation on interconnect performance will continue to increase. Graphene has attracted much interest as a replacement for copper interconnects due to its large conductivity and high current-carrying capacity [1<\/a>]<\/sup> [2<\/a>]<\/sup> [3<\/a>]<\/sup>. Graphene sheets are also an attractive alternative to carbon nanotube-based interconnects as they are more compatible with conventional lithography methods. This project focuses on integrating high-density graphene devices and characterizing their properties as global interconnects.<\/p>\n