{"id":398,"date":"2010-06-23T11:08:57","date_gmt":"2010-06-23T15:08:57","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=398"},"modified":"2010-07-26T12:04:03","modified_gmt":"2010-07-26T16:04:03","slug":"vladimir-stojanovic","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/vladimir-stojanovic\/","title":{"rendered":"Vladimir Stojanovic"},"content":{"rendered":"<div class=\"page-restrict-output\"><h3>Collaborators<\/h3>\n<ul>\n<li>E. Alon, UC Berkeley<\/li>\n<li>K. Asanovic, UC Berkeley<\/li>\n<li>T.-J. King Liu, UC Berkeley<\/li>\n<li>A. Kavcic, U. Hawaii at Manoa<\/li>\n<li>D. Markovic, UC Los Angeles<\/li>\n<li>C-K. K. Yang, UC Los Angeles<\/li>\n<\/ul>\n<h3>Graduate Students<\/h3>\n<ul>\n<li>W. An, EECS<\/li>\n<li>F. Chen, Research Assistant, EECS<\/li>\n<li>H. Fariborzi, Research Assistant, EECS<\/li>\n<li>M. Georgas, Research Assistant, EECS<\/li>\n<li>J. Leu, Research Assistant, EECS<\/li>\n<li>Y. Li, Research Assistant, EECS<\/li>\n<li>B. Moss, Research Assistant, EECS<\/li>\n<li>S. Song, Research Assistant, EESC<\/li>\n<li>R. Sredojevi\u0107, Research Assistant, EECS<\/li>\n<li>C. Sun, Research Assistant, EECS<\/li>\n<li>O. Uyar, Research Assistant, EECS<\/li>\n<\/ul>\n<h3>Publications<\/h3>\n<p>C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovi\u0107, and K. Asanovic,<em> <\/em>\u201cBuilding manycore processor to DRAM networks with monolithic CMOS silicon photonics [Invited],\u201d <em>IEEE Micro, <\/em>vol. 29, no. 4, pp. 8-21, 2009.<\/p>\n<p>N. Blitvic, M. Lee, and V. Stojanovi\u0107, \u201cChannel Coding for High-speed Links: A systematic look at code performance and system simulation [Invited],\u201d <em>IEEE Transactions on Advanced Packaging<\/em>,<em> <\/em>vol. 2, no. 32, pp. 268-279, 2009.<\/p>\n<p>K.S. Oh, F. Lambrecht, S. Chang, Q. Lin, J. Ren, C. Yuan, J. Zerbe, and V. Stojanovi\u0107, \u201cAccurate System Voltage and Timing Margin Simulation in High-Speed I\/O System Design,\u201d <em>IEEE Transactions on Advanced Packaging, <\/em>vol. 31, no. 4, pp. 722-730, 2008.<em> <\/em><\/p>\n<p>B. Kim and V. Stojanovi\u0107, \u201cModeling and Design Framework: Equalized and Repeated Interconnects for Networks-on-Chip [Invited],\u201d <em>IEEE Design &amp; Test of Computers, <\/em>vol. 25, no. 5, pp. 430-439, 2008.<\/p>\n<p>T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. K\u00e4rtner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, &#8221; Silicon photonics for compact, energy-efficient interconnects [Invited],&#8221; J. Opt. Netw. <strong>6<\/strong>, 63-73 (2007)<\/p>\n<p>F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J.\u00a0Jeon, T-J. K. Liu, D. Markovi\u0107, V. Stojanovi\u0107, and E. Alon, \u201cDemonstration of Integrated Micro-Electro-Mechanical (MEM) Switch Circuits for VLSI Applications,\u201d <em>IEEE International Solid-State Circuits Conference<\/em>, San Francisco, CA, pp. 150-151, February 2010.<\/p>\n<p>J. S. Orcutt, A. Khilo, M. A. Popovi\u0107, C. W. Holzwarth, H. Li, J. Sun, B. Moss, M. S. Dahlem, E. P. Ippen, J. L. Hoyt, V. Stojanovi\u0107, F. X. Kartner, H. I. Smith, R. J. Ram, \u201cPhotonic integration in a commercial scaled bulk-CMOS process,\u201d <em>IEEE International Conference on Photonics in Switching<\/em>, Pisa, Italy, pp. 1-2, September 2009.<\/p>\n<p>F. Chen, A. Chandrakasan, and V. Stojanovi\u0107, \u201cAn Oscilloscope Array for High-Impedance Device Characterization,\u201d <em>European Solid-State Circuits Conference, <\/em>Athens, Greece, 4 pages, September 2009.<\/p>\n<p>A. Joshi, B. Kim, and V. Stojanovi\u0107,\u201dDesigning Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,\u201d<em> IEEE Symposium on High-Performance Interconnects, <\/em>New York, NY, 10 pages, August 2009.<\/p>\n<p>Y. Li and V. Stojanovi\u0107, \u201cYield-driven Iterative Robust Circuit Optimization Algorithm,\u201d <em>ACM\/IEEE Design Automation Conference<\/em>, San Francisco, CA, 6 pages, July 2009.<\/p>\n<p>S.Song, B. Kim, and V. Stojanovi\u0107, \u201cA Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion,\u201d <em>IEEE<\/em> <em>Symposium on VLSI Circuits<\/em>, Kyoto, Japan, pp. 222-223, June 2009<em>.<\/em><\/p>\n<p>A. Joshi, C. Batten, Y-J. Kwon, S. Beamer, K. Asanovi\u0107, and V. Stojanovi\u0107, \u201cSilicon-Photonic Clos Networks for Global On-Chip Communication,\u201d 3rd ACM\/IEEE International Symposium on Networks-on-Chip, San Diego, CA, pp. 124-133, May 2009.<\/p>\n<p>B. Kim and V. Stojanovi\u0107, \u201cA 4 Gb\/s\/ch 356fJ\/b 10 mm Equalized On-Chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90 nm CMOS Technology,\u201d <em>IEEE International Solid-State Circuits Conference<\/em>, San Francisco, CA, pp. 66-67, February 2009.<\/p>\n<p>R. Sredojevi\u0107 and V. Stojanovi\u0107, \u201cOptimization-based Framework for Simultaneous Circuit and System Design-Space Exploration: A High-Speed Link Example,\u201d <em>IEEE\/ACM International Conference on Computer-Aided Design, <\/em>San Jose, CA, pp. 314-321, November 2008.<\/p>\n<p>F. Chen, H. Kam, D. Markovi\u0107, T.J. King, V. Stojanovi\u0107, and E. Alon, \u201cIntegrated Circuit Design with NEM Relays,\u201d <em>IEEE\/ACM\u00a0 International Conference on Computer-Aided Design<\/em>, San Jose, CA, pp. 750-757, November 2008.<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"<div class=\"page-restrict-output\"><p>On-chip interconnects and high-speed off-chip interfaces (electrical, photonic). Circuit and interconnect design with novel devices (CNTs, NEM relays, Si-photonics). Modeling and analysis of noise and dynamics in circuits and systems. Application of optimization techniques to digital communications, analog and digital circuits. Digital communications and signal-processing architectures, clock generation and distribution, high-speed digital circuit design, VLSI and mixed-signal IC design.<\/p>\n<\/div>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[80],"tags":[18,68],"_links":{"self":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/398"}],"collection":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/comments?post=398"}],"version-history":[{"count":2,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/398\/revisions"}],"predecessor-version":[{"id":2286,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/398\/revisions\/2286"}],"wp:attachment":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/media?parent=398"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/categories?post=398"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/tags?post=398"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}