{"id":2078,"date":"2010-07-14T13:10:28","date_gmt":"2010-07-14T17:10:28","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=2078"},"modified":"2010-07-19T12:07:43","modified_gmt":"2010-07-19T16:07:43","slug":"active-photonics-in-a-cmos-platform","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/active-photonics-in-a-cmos-platform\/","title":{"rendered":"Active Photonics in a CMOS Platform"},"content":{"rendered":"

Although the majority of silicon photonic research is motivated by end applications where photonic devices can be integrated alongside millions of transistors, most research devices are fabricated in independent photonics-only process flows. Free from the constraints of working within an existing process, fabrication steps and layer geometries have been tailored to optimize the performance of individual devices. The short-flow methodology has enabled pioneering device research and proof-of-concept demonstrations by many academic and industrial groups [1<\/a>]<\/sup>. The rapid progress in this work helped to lay the groundwork for the demonstration of a complete electronic-photonic integrated circuit (EPIC) platform by modifying a 130-nm SOI-CMOS platform to accommodate the required fabrication steps [2<\/a>]<\/sup>. Today, however, prominent EPIC applications from multiprocessor interconnect [3<\/a>]<\/sup> to coherent-communication receivers [4<\/a>]<\/sup> require photonic devices to be integrated alongside the dense, high-performance transistors available only within state-of-the-art electronic processes. Recently, localized substrate-removal technology has enabled photonic device integration through the addition of a single post-fabrication step on designs fabricated in unmodified state-of-the-art CMOS electronic foundries [5<\/a>]<\/sup>. By sharing all in-foundry processes, EPICs including state-of-the-art transistors can leverage the existing infrastructure and economy of scale provided by the orders-of-magnitude-larger electronics industry. The major constraint is to adapt the photonic device designs to be manufacturable within the existing process. This challenge is illustrated by comparing the scaled CMOS lateral p-i-n diode shown in Figure 1a to existing p-i-n diodes used as modulators within traditional silicon photonics processes shown in Figure 1b-d. Although the diode formed is electrically suitable for use as a carrier-injection modulator, the slab geometry does not allow for lateral optical confinement away from the optically-lossy electrical contacts. Therefore, novel diode design, perhaps including non-uniform patterning in the direction of propagation, is required to reduce integrate contacts with low optical loss.<\/p>\n

\"Figure<\/a><\/p>\n

Figure 1: (a) Slab waveguide CMOS modulator cross-section differs greatly from the geometries of previously demonstrated silicon modulators: (b) injection-mode rib waveguide p-i-n diode [1<\/a>]<\/sup>, (c) depletion-mode vertical junction rib waveguide [6<\/a>]<\/sup>, and (d) depletion-mode vertical junction slab waveguide diode [7<\/a>]<\/sup>.<\/p>\n<\/div>\n

\r\nReferences
  1. Q. Xu et al., \u201cMicrometre-scale silicon electro-optic modulator,\u201d in Nature<\/em> 435, 325-327, (2005). [↩<\/a>] [↩<\/a>]<\/li>
  2. C. Gunn, “Fully integrated VLSI CMOS and photonics ‘CMOS photonics’,” in VLSI Technology, 2007 IEEE Symposium on, 6-9 (2007). [↩<\/a>]<\/li>
  3. C. Batten et al., \u201cBuilding many-core processor-to-DRAM networks with monolithic CMOS silicon photonics,\u201d IEEE Micro<\/em> 29, 8-21 (2009). [↩<\/a>]<\/li>
  4. C.R. Doerr et al., \u201cMonolithic polarization and phase diversity coherent receiver in silicon,\u201d J. Lightwave Technol<\/em>. 28, 520-525 (2010). [↩<\/a>]<\/li>
  5. C.W. Holzwarth et al., \u201cLocalized substrate removal technique enabling strong-confinement microphotonics in a bulk CMOS process,\u201d in Proc. CLEO\/IQEC Conf. Lasers Electro Opt\/Intl. Quant. Elec. Conf<\/em>., Mar. 2008. [↩<\/a>]<\/li>
  6. A. Liu et al., “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt. Express<\/em> 15, 660-668, (2007). [↩<\/a>]<\/li>
  7. M.R. Watts, D.C. Trotter, and R.W. Young, “Maximally confined high-speed second-order silicon microdisk switches,” in Proc. Optical Fiber Communication Conf<\/em>., Feb. 2008. [↩<\/a>]<\/li><\/ol><\/div>","protected":false},"excerpt":{"rendered":"

    Although the majority of silicon photonic research is motivated by end applications where photonic devices can be integrated alongside millions…<\/p>\n<\/div>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[12],"tags":[4224,63],"_links":{"self":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/2078"}],"collection":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/comments?post=2078"}],"version-history":[{"count":7,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/2078\/revisions"}],"predecessor-version":[{"id":2204,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/2078\/revisions\/2204"}],"wp:attachment":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/media?parent=2078"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/categories?post=2078"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/tags?post=2078"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}