{"id":1884,"date":"2010-07-13T14:42:15","date_gmt":"2010-07-13T18:42:15","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=1884"},"modified":"2010-07-13T16:42:51","modified_gmt":"2010-07-13T20:42:51","slug":"sub-30-nm-patterning-of-au-on-gaas-substrates","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/sub-30-nm-patterning-of-au-on-gaas-substrates\/","title":{"rendered":"Sub-30-nm Patterning of Au on GaAs Substrates"},"content":{"rendered":"
In this work, we demonstrated the patterning of Au features on <111> B GaAs substrates by galvanic displacement and metal evaporation into sub-30-nm pores in a silicon oxide hard mask layer. Patterning of small Au features onto GaAs substrates is of particular interest due to their use as metal catalysts for GaAs and GaAs-alloy nanowire growth. Semiconducting nanowires have a variety of potential applications, such as field-effect transistors (FETs) [1<\/a>]<\/sup>, and their size-dependent properties have been exploited for a variety of optoelectronic devices [2<\/a>]<\/sup>. However, much work remains to create lithographically-templated nanowires for integration into future manufacturing processes.<\/p>\n