{"id":1546,"date":"2010-07-08T13:57:11","date_gmt":"2010-07-08T17:57:11","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=1546"},"modified":"2010-07-19T11:22:19","modified_gmt":"2010-07-19T15:22:19","slug":"design-and-demonstration-of-integrated-micro-electro-mechanical-mem-relay-circuits-for-vlsi-applications","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/design-and-demonstration-of-integrated-micro-electro-mechanical-mem-relay-circuits-for-vlsi-applications\/","title":{"rendered":"Design and Demonstration of Integrated Micro-electro-mechanical (MEM) Relay Circuits for VLSI Applications"},"content":{"rendered":"

Silicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to subthreshold leakage. Once this limit is reached, power constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate device with steeper sub-threshold slope \u2013 i.e., lower VDD<\/sub>\/Ion<\/sub> for the same Ion<\/sub>\/Ioff <\/sub>((H. Kam, et al., \u201cCircuit Level Requirements for MOSFET Replacement Devices,\u201d in IEDM Tech. Dig.<\/em>, 2008, pp. 427.)). One promising class of such devices is electro-statically actuated micro-electro-mechanical (MEM) relays with nearly ideal Ion<\/sub>\/Ioff<\/sub> characteristics. Although mechanical movement makes MEM relays significantly slower than CMOS, they can be useful for a wide range of VLSI applications by reexamining traditional system- and circuit-level design techniques to take advantage of the electrical properties of the device. Unlike in CMOS circuit design, logic functions in MEMS circuit design should be implemented as a single complex gate with minimum-sized relays, resulting in significantly reduced logic complexity. We have recently shown that with optimized circuit topologies MEM relays may potentially enable ~10x lower energy over CMOS at up to ~0.1-1GHz frequencies [1<\/a>]<\/sup>. This work takes initial steps towards experimental validation of these principles by leveraging recently developed relay technology and reliability enhancements [2<\/a>]<\/sup> [3<\/a>]<\/sup> to demonstrate several monolithically integrated MEM relay-based building blocks. Specifically, our chip includes logic, memory, I\/O, and clocking structures, and we demonstrate successful basic functionality and circuit composition [4<\/a>]<\/sup>. These relay circuits illustrate a range of important functions necessary for the implementation of integrated VLSI systems, and give insight into circuit design techniques that leverage the physical properties of these devices.<\/p>\n\n\t\t