{"id":1321,"date":"2010-07-02T14:47:41","date_gmt":"2010-07-02T18:47:41","guid":{"rendered":"https:\/\/wpmu2.mit.local\/?p=1321"},"modified":"2010-07-02T14:48:04","modified_gmt":"2010-07-02T18:48:04","slug":"a-novel-platform-for-monolithic-integration-of-iii-v-devices-with-si-cmos-technology","status":"publish","type":"post","link":"https:\/\/wpmu2.mit.local\/a-novel-platform-for-monolithic-integration-of-iii-v-devices-with-si-cmos-technology\/","title":{"rendered":"A Novel Platform for Monolithic Integration of III-V Devices with Si CMOS Technology"},"content":{"rendered":"
\"Figure<\/a>

Figure 1: TEM micrograph of the SOLES structure.<\/p><\/div>\n

Silicon-on-lattice-engineered-substrates (SOLES), shown in Figure 1, were developed in our group as a substrate platform for integrating III-V devices with Si CMOS technology [1<\/a>]<\/sup> [2<\/a>]<\/sup>.\u00a0 The SOLES wafer consists of a Si-on-insulator layer on top of a buried Ge-on-insulator structure.\u00a0 The Ge layer provides a template for III-V growth and device processing [3<\/a>]<\/sup> [4<\/a>]<\/sup>.\u00a0 Si CMOS devices can be processed on the SOI layer [4<\/a>]<\/sup>.\u00a0 Because traditional Si device processing typically involves high temperature steps, the total thermal budget allowed by the SOLES wafer was carefully evaluated.\u00a0 No morphological changes were seen in the SOLES wafers after anneals of up to 915\u00b0C.\u00a0 However, Ge agglomeration and film delamination were present in samples annealed at temperatures approaching Ge\u2019s melting point, limiting the allowed thermal budget of the SOLES wafer [5<\/a>]<\/sup>.\u00a0 A sustained 915\u00b0C anneal did result in Ge diffusion, leading to an accumulation of Ge at the Si-SiO2<\/sub> interfaces (see Figure 2) [5<\/a>]<\/sup>.\u00a0 This accumulation could lead to deleterious effects on the Si CMOS devices.\u00a0 To date, CMOS device processing with a properly designed thermal budget that limits Ge diffusion has be used to process devices on SOLES [4<\/a>]<\/sup>.\u00a0 In order to increase the flexibility of the SOLES wafer, a SiNx<\/sub> layer as thin as 250\u00c5 can be embedded in the SiO2<\/sub> in order to block Ge diffusion to the top Si (see Figure 2) [5<\/a>]<\/sup>.\u00a0 Currently, research is underway toward the next generation of SOLES, including fabrication of low threading dislocation density GaAs-OI and InP-OI.\u00a0 Contact metallurgies to III-V materials that are compatible with Si processing are also being investigated.<\/p>\n

\"Figure<\/a>

Figure 2: SIMS profile of Ge concentration after 8.5h 915\u00b0C anneal in SOLES structure (red), in modified structure with 1000\u00c5 (blue) and 250\u00c5 (pink) of SiNx embedded in the SiO2. <\/p><\/div>\n

\r\nReferences
  1. C. L. Dohrman, K. Chilukuri, D. M. Isaacson; M. L. Lee, and E. A. Fitzgerald, \u201cFabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices<\/a>,\u201d\u00a0 Materials Science and Engineering B: Solid-State Materials for Advanced Technology, <\/em> vol. 135, no.3, pp. 235-237, Dec. 2006. [↩<\/a>]<\/li>
  2. F. Letertre, \u201cFormation of III-V Semiconductor Engineered Substrates Using Smart CutTM<\/sup> Layer Transfer Technology,\u201d in Mater. Res. Soc. Symp. <\/em>Proc. 2008<\/em>, vol. 1068, pp. 1068-C01-01. [↩<\/a>]<\/li>
  3. K. Chilukuri, M. J. Mori, C. L. Dohrman, E. A. Fitzgerald, \u201cMonolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES)<\/a>,\u201d Semiconductor Science and Technology<\/em>, vol. 22, pp. 29-34, 2007. [↩<\/a>]<\/li>
  4. W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W.\u00a0 Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, N. Daval, \u201cMonolithic integration of InP-based transistors on Si substrates using MBE,\u201d J. Crystal Growth<\/em>, vol. 311, no. 7, pp. 1979\u20131983, Mar. 2009. [↩<\/a>] [↩<\/a>] [↩<\/a>]<\/li>
  5. N. Yang, M. T. Bulsara, E. A. Fitzgerald, W.K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wu, M. Urteaga, W. Ha, J. Bergman, B. Brar, C. Drazek, N. Daval, L. Benaissa, E. Augendree W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior, \u201cThermal Considerations for Advanced SOI Substrates Designed for III-V\/Si Heterointegration,\u201d in 2009 IEEE International SOI Conference<\/em>, pp. 121-122, Oct. 2009. [↩<\/a>]<\/li><\/ol><\/div>","protected":false},"excerpt":{"rendered":"

    Silicon-on-lattice-engineered-substrates (SOLES), shown in Figure 1, were developed in our group as a substrate platform for integrating III-V devices with…<\/p>\n<\/div>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[8],"tags":[19,4141],"_links":{"self":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/1321"}],"collection":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/comments?post=1321"}],"version-history":[{"count":43,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/1321\/revisions"}],"predecessor-version":[{"id":1366,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/posts\/1321\/revisions\/1366"}],"wp:attachment":[{"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/media?parent=1321"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/categories?post=1321"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/wpmu2.mit.local\/wp-json\/wp\/v2\/tags?post=1321"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}